Present (via video links & telephone)

CERN: R. Bock, R. McLaren, M. Mueller, R. Scholte, H. Singpiel, J. Strong, E. van der Bij, J. Vermeulen
RHUL: B. Green
SACLAY: M. Huet, I. Mandjavidze, D. Calvet
UCL: R. Cranfield, P. Clarke
WEIZMANN: L. Levinson (phone)
NIKHEF: H. Boterenbrood, P. Jansweijer, G. Kieft

Notes by R. Cranfield and J. Vermeulen

1. New information concerning the parameters (J. Vermeulen) (slides)

The  presentation of the last meeting was updated. New data for Pixels & SCT from Nick Ellis have led to new estimates for minimum and maximum data rates, in particular the low luminosity data rate is at maximum ~6 MB/s per ROBIn rather than ~18MB/s due to changes for SCT and pixel event fragment sizes.

NB The slides reflect the status at the time of the meeting. See the modelling page for the latest version of the spreadsheet and of the paper model document.

2. Status updates

NIKHEF: (J. Vermeulen)

Five ShaSLINK(Sharc + Slink source+ PCI interface) boards have been produced and tested (slides). They are functioning according to the specifications. Transfer speeds up to 160 MByte/s via S-link and up to 130 MB/s via PCI bus have been observed.

A ROB Complex with a SHaSLINK as output part and CRUSHes as ROBIns has been set up. With 1 or 2 ROBIns this functions as it should, the setup was being tested with 4 ROBIns (simulated by 2 CRUSHes) at the time of the meeting.

Further results of performance measurements of the CRUSH (slides), including comparison with formulae, were reported. It was mentioned that it will be tried to set up a (computer) model.

UK: (R. Cranfield)

The ROB-in has been integrated into the DAQ-1 setup and is working, performance measurements were reported to be underway.

The results of measurements for characterizing the performance of ROB-in done in the UK were reported to be analysed.

For both sets of measurements the SLIDAS source is used.

Mannheim : (M. Mueller) (slides)

The Atlantis Computing Board is finished and reported to be available in CERN, with the integration into the testbed software being tested.
The Atlantis I/O board should be available by December. Effort with respect to the ROBIns is focussed on Atlantis: further developments concerning application of the microEnable as ROBIn were mentioned to be unlikely.

Saclay: (M. Huet, I. Mandjavidze)

It was found that the new ROBIN design did not  fit in 2 FPGAs (Mach devices) so it was modified for 3 FPGAs. 10 pieces are planned to be ready by the end of the year (slides).

More sophisticated event management has been introduced in the Mark1 ROBIN (hashing mechanism: chains of event descriptors pointed to in hash table, with desriptors of events released returned to free list). In a Compact PCI environment and with a 200 MHz Pentium as ROB Controller measurements have been made (slides).

SLIDAS (E. van der Bij) (slides)

The set of agreed modidifications was made to the SLIDAS this summer. The modifications include:
* new data block sizes,
* frequency at which blocks are send can be adjusted,
* external trigger with buffering,
* overflow status on LEDs.

S-Link (R. McLaren)

The high-speed version (utilizing 2 G-links) is being worked on and is hoped to be available before the end of the year.

3. Suggestions for scenarios

NB See also the documents produced after the meeting available via the ROBComplex page

NIKHEF (J. Vermeulen) (slides)

Two main scenarios, both based on the SHARC processor, were described :

First scenario: VME boards with SHARC based ROBIns (6 or 4 per board) connecting to RIO2 like processors in VME crates, where the "RIO2s" interface (via PMC cards) to the LVL2 and EB networks. For 3 different configurations the number of components required have been  calculated with the paper model .

Second scenario: no direct connection to LVL2 and EB networks, but via S-Links to LVL2 farm processors (which are connected to the LVL2 network) and via other S-links to the DAQ system. This "intermediate ROB" or "iROB" scenario could take care of partial RoI fragment and event building and could make use of 9U VME crates (128 ROBIns per crate). It also allows decoupling of the LVL2 and DAQ EB systems. Extending the system with a modified version of the "iROB crates" could allow to perform complete RoI fragment building and event building with an additional 4 crates.

UK (R. Cranfield) (extended description)

A "simple-ROB" scenario was described, which goes back to the original ROB concept  and is in fact the limiting case of  a ROB Complex with a single ROBIn. It was noted that the advantages of the ROB Complex concept remain to be proved; meanwhile networking costs are coming down so that it is plausible to consider using a switch for all communications. Assuming the use of Fast or Gigabit Ethernet simple-ROBs will need up to 2 Fast Ethernet connections or 1 Gigabit Ethernet connection. Simple ROBs could be packed physically similar to the packing used for a ROB Complex, possibly 6 - 12 on a 9U board. It is desirable to have an auxiliary connection for a group of ROBs for control & monitoring.

Saclay (I. Mandjavidze) (slides)

Modelling results imply to group either a low(2), a medium or a high (~12)  number of ROBins per ROB Complex. Compact PCI crates with 2 busses of 8 slots each, interconnected by a bridge, could support 2 ROB Complexes per  crate for low and medium number of ROBIns, and 1 ROB Complex per crate for large number of ROBins. Compact PCI crates can be 3U or 6U high and is an industry standard.

It was questioned whether the event size is really 2kByte and whether full event building always is necessary in view of the high bandwidth requirements.

Mannheim (M. Mueller)

As described in earlier meetings : The ATLANTIS I/O board supports 4 input M-links, up to 8 of these boards can be used per (Compact PCI) crate, the ROB controller is a PC (Compact PCI board), the output is via a standard network interface.

CERN (R. Bock)

It was remarked that the scattering of information in the ROBs forms a problem with off the shelf hardware and software. An intelligent ROB Complex could be based on a COTS SMP system. These are currently available with many PCI slots and up to 8 processors. With a large enough complex feature extraction could be feasible, but in any case RoI fragment building would imply much reduced message frequencies in the LVL2 network. Offers of help from Mannheim (microEnable), US (MSU, software) and CERN (funding) have been received for demonstration with a system having 4 500 MHz Xeon processors. Help with modelling will be provided by S. Wheeler and J. Vermeulen..

J. Vermeulen noted that his 2nd scenario is similar with data in a SMP system input via S-link instead of via a number of PCI cards.

Discussion

R. McLaren remarked that there is a need to provide estimates of costs, risks, timescales, etc

R. Cranfield : are the relevant issues listed in the Master Working Document ? It needs to be decided how to structure the document (issues within scenarios, or each issue referring to the various scenarios).

The first step is for presenters to send written versions of the above descriptions to convenors by 25-September (see ROB page for these documents).

4. Next meeting, MWD, contacts with DAQ-1, AOB

Next meeting

The next meeting was planned to be a face-to-face meeting of at least one day at the end of October. The location could be either in the UK (there was an invitation from RHUL) or CERN, to be decided in the week after the meeting. (The decision was : next meeting in CERN at 3 November 1999 starting at 9.00 for the full day). Main agenda items are measurement results, and convergence to final documentation. For both, input is requested in time (27 October) for people to digest before the meeting.

MWD

The editors need to collaborate on updating the Master Working Document . Scenarios, measurements, and modelling results have to be incorporated. L.Levinson will proceeed to gather detector information (in good time for the next meeting). It is the aim to circulate a new edition of the MWD before the next meeting.

Contacts with DAQ-1

J. Vermeulen expressed his concern about the interaction with the DAQ Group. There are no further meetings planned. At the last meeting with DAQ the DAQ representatives had been reluctant to agree another meeting, preferring to wait for the TDSG to organise a structure for preparation of the TP. It is still unclear how this will proceed. J. Vermeulen noted that his 2nd scenario allows for an architecture that decouples LVL2 from DAQ. R. Cranfield thought it would be a great pity if the architecture ends up being chosen on political grounds!

AOB

i) We should consider how we propose to cope with operating the ROBs in the absence of  central trigger processing (e.g. in detector commissioning). In principle this does not seem problematic, but the MWD should describe the options. One possibility is to use the TTC system, which will anyway carry the triggers for individual sub-detector partitions. J. Vermeulen noted that he planned to raise this issue at the integration meeting of September 10.
ii) It is important for upcoming discussions that we continue to develop a UML description of the LVL2 approach(es) to ROBs. M. Huet has been doing some more work on this. He will distribute his updated diagrams to relevant people so we can try to agree a generic description. He will also contact D. Francis. We should aim to have something to agree by the next meeting.
iii) One of the main outputs from the ROB Complex studies is meant to be input for a revision of the URD. The status of this document, and arrangements for its revision, are unclear (especially since the departure of the main maintainer). We should clarify the plans for documenting user requirements. J. Vermeulen noted that this is another item for discussion in the integration meeting.