The processing in the HADC unit occurs in three steps. The first of these is the triggering of the module, described in section 1. This starts the digitization process. After this the module prepares for read-out with the construction of the header words, described in section 2. Based on externally provided pulses, the choice is made to either delete (upon receipt of a reject pulse) or put the data ready for read-out (on receipt of an accept pulse). The final step is the read-out by the VME-controller (section 4).
back to topThe HADC consists of two halves, each with its own timing and each equipped with two ADC channels. The timing between the two halves is different in order to allow the optimization of the analog to digital conversion to the slightly different timing of the two sides of the silicon detector. This difference is caused by the different mobilities of electrons and holes in the silicon.
The triggering within one half of the HADC is a combination of three signals: the external trigger provided to the module via the frontpanel, and the outputs of two discriminators, which look at the inputs of the two ADC channels within this half. The logical function combining these signals can be programmed. The timing of the signals should normally be such that the external trigger enables the discriminator signals. The triggers of the two halves of the HADC are combined to start the data acquisition process in the module. The trigger is stretched to envelope the signal from the HELIX, i.e. to a length of 60 µs (624 clock periods consisting of 128 data channels plus 8 trailers per HELIX, four HELIXes, and 80 clock ticks for the common mode process and overhead. The exact value depends on the datavalid delay, in this number the max delay is assumed).
When the trigger forms, space is claimed in the memory for the data which will be produced. This is visible in the ModeStatusRegister (bits 20..22, events stored). During the digitization this memory is filled with data. When the (stretched) trigger runs out, the data that end up in the first headerword are known and the next phase begins.
back to topAfter completion of the digitization the number of output words is known. This appears together with some other items in the first headerword. To be prepared for the read-out this headerword is constructed on the trailing edge of the stretched trigger or when te accept pulse (see below) is received. The result is written in memory and no further action is taken. This completes the acquisition part of the event cyclus.
The fate of the data collected in the acquisition part is decided here. There is the choice between two options, which must be made by pulsing exactly one of the accept and reject inputs for each trigger. This must happen at least 6 clock cycles (0.55 µs) after the leading edge of the trigger, and before the read-out is initiated. A more practical higher limit is the end of the stretched trigger. The choice is stored in a FIFO in the same order as the trigger which must have occurred before the accept or reject pulses. If no such trigger has been received the pulses are ignored. When the module is ready to process the data from the next trigger, this choice is retrieved from the FIFO, and depending on its contents the memory occupied by the data is freed (and the events stored-counter in the ModeStatusRegister decremented) in the case of a reject, or the module waits for a read-out cycle from the VME-controller in the case of an accept.
back to topThe final step is the read-out of the data. This phase is entered after a successful completion of the acquisition phase, and the receipt of an accept pulse. The read-out mechanism implemented is the mechanism in the STRUCK725 which is called pcos. The module presents itself as a FIFO to be read out in VME-block mode on address n*0x10000, where n is taken from 0, 1, 2, etc. The module tells the controller that it is empty by asserting the IRQ6 or IRQ7 interrupt lines during the last data transfer. If the controller detects an IRQ6 it increments the address by 0x10000 thus addressing the next module. However, when an IRQ7 is detected the controller knows that no more modules have to be read-out and therefore finishes its operations for this event.
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