Front-End Electronics

Constraints for preamplifier, pipeline and buffer:

• dc or ac coupled
• pitch value related to the pitch of the detector chips
• peak time of the preamplifier less than time in between crossings: 96 ns
• coupling to first-level clock of 10.42 MHz
• optional running standalone with self provided clock
• for binary:  controllable threshold
• data of crossing to be stored for L1 latency of 5 microseconds
• storage of data (current plus previous and next crossing) in secondary buffer within 8 microseconds after L1 (to be specified further)
• to be ready for new storage of data within 8 microseconds after L1
• reporting of buffer full and pipeline not able to store data in secondary buffer
• resetting of pipeline on receipt of first-level trigger reset
• zeroing of permanent noisy channels on run-by-run basis
• being immune to single-point failures
• error status to be reported
• test pulses at various levels to determine the noise level and the working of the system

Data Transfer

• transfer rate of 1 kHz of data to read-out boards in the rucksack. If we don't use the data in a second-level trigger the rate just can be 100 Hz, if enough buffering is supplied
• transfer over 80 meters
• include data compression /sparsification (switchable) for rejecting non-physical signals
• immune to transmission errors: loss of data allowed, but not blocking of the datastream
• tentative maximum transfer rate  (very preliminary since data formats are not defined yet):

  binary:

  1. a maximum occupancy of 3% (?) per detector  chip  of 128 channels
  2. include data of  nearest neighbours
  3. 3-bit data word for present, previous and next 'bunch'
  4. an overhead of 6-bits per packet and 8-bits  address per dataword

  So maximum transfer needed per chip is: 0.03*128*(6 + 3 * (8 + 3))*1000 = 150 kbit/s, excluding data of neighbours: 65 kbit/s.

  analog:

  as above for 8-bit readout after adc per chip: 0.03*128*(6 + 3 * (8 + 3*8))*1000 = 390 kbit/s, excluding neighbours: 146 kbit/s.

VME-Buffers

The data transmitted over the links are stored in Readout Modules:

• storage of data after L1 in 20 events deep buffers
• readout via VME after L2 decision
• data of a crate to be readout within 2 milliseconds
• aborting of readout or data transfer from front-end after receipt of Fast-Clear within 25 microseconds after L1

If used in combination with the 2TP-module, further requirements for the readout modules are:

• raising interrupt after getting data
• interrupts of readout modules are daisy-chained
• readout modules should provide status, including errors, first-level trigger number, first-level trigger type
• paging of output
• write possibility of pages by transputer

In this view the 2TP-module will be the interface to the event-builder and the second-level trigger. Therefore the implications can be ignored here.

Second-Level Trigger

Requirements are:

• interface at VME-level
• data to be provided within a few hundred microseconds after L1

Power Supplies

The power supplies have to deliver power both to detectors and electronics. The requirements for stability and amount of power have to be established. The steering should fit into the normal ZEUS framework of Slow-Control.

Concerning this subject BaBar mentions: "The power supply system must provide the voltages for both the silicon detectors and the front-end chips and opto-electronics. The low-noise electronic readout imposes stringent requirements on the power supplies. they must be carefully designed to prevent common-mode noise from entering the system.

Both supply subsystems must be build up from modular, fully floating units without galvanic connection between the utility side and the load side, with the two sides electrostatically shielded. Preference is generically given to continuous-type voltage regulators in view of their lower noise levels. However, tests should be done to determine whether smaller switching regulators with better power yield can also provide satisfactory performance.

The power supplies must also feature remotely controlled, digitally preset voltages. Optical connection of the voltage controls is recommended. The power supplies must be capable of sweeping the output voltage throughout the nominal range as specified below.

The specifications for the two different supply subsystems are as follows. For the detector bias supply, the nominal full scale voltage is 80 V per module, with a setting resolution of 7 bits and maximum current of 0.1 A. Ripple must be less than 10 mV peak to peak, and noise must be less than 2 mV rms. For the electronics power supply, the nominal full scale voltage is 6 V per module, with a setting resolution of 8 bits ad maximum current of 100 A. Ripple must be less than 2 mV peak to peak, and noise must be less than 500 microV rms."

Please mail suggestion/corrections/updates to Leo Wiggers (wiggers.nikhef.nl)